1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device preferable for forming wiring layers.
2. Description of the Related Art
A damascene method is known as a method of forming Cu wirings. FIGS. 12A to 12J are cross sectional views showing a conventional method of fabricating a semiconductor device in the order of processing.
In the conventional method, as shown in FIG. 12A, a low dielectric constant film 101 and a SiC film 103 are formed on an interlayer insulating film and the like, and wiring trenches are formed in the low dielectric constant film 101 and the SiC film 103. And, wirings 102 are buried in the wiring trenches.
Next, a stopper film 104 and a low dielectric constant film 105 are formed on the wirings 102 and the SiC film 103. As the stopper film 104, a SiCH film is formed, for example. As the low dielectric constant film 105, a SiOCH film is formed, for example.
Next, a low dielectric constant film 106 is formed on the low dielectric constant film 105 by a coating method. As the low dielectric constant film 106, a porous silica film (NCS (Nano Clustering Silica) film, for example) is formed, for example.
Thereafter, a hardmask 107, a hardmask 108, and a hardmask 109 are formed in this order on the low dielectric constant film 106. As the hardmask 107, a SiCH film is formed, for example. As the hardmask 108, a SiO2 film is formed, for example. As the hardmask 109, a SiC film is formed, for example.
Next, as shown in FIG. 12B, a resistmask 110 having a pattern with via holes is formed on the hardmask 109.
Next, as shown in FIG. 12C, via holes 111 which extend to the middle of the low dielectric constant film 105 are formed in the hardmask 109, the hardmask 108, the hardmask 107, the low dielectric constant film 106 and the low dielectric constant film 105 using the resistmask 110 as a mask.
Next, as shown in FIG. 12D, the resistmask 110 is removed by ashing. Thereafter, residues are removed by performing wet process.
Next, by burying resin material into the via holes 111, and by etching back it using O2 plasma, as shown in FIG. 12E, resin films 113 are formed in the via holes 111, and its surface is flattened. Next, an anti-reflection film 114 and a resistmask 115 having a pattern of wirings are formed in this order over the whole surface.
Next, as shown in FIG. 12F, patterning of the anti-reflection film 114 and the hardmask 109 is performed using the resistmask 115 as a mask. At this time, the upper surface of the resin film 113 goes down.
Thereafter, as shown in FIG. 12G, the resistmask 115 and the anti-reflection film 114 are perfectly removed by ashing.
Next, as shown in FIG. 12H, patterning of the hardmask 108 and the hardmask 107 is performed using the hardmask 119 as a mask, and the via holes 111 are extended to the stopper film 104. As a result, the hardmask 109 vanishes.
Next, as shown in FIG. 12I, by patterning the low dielectric constant film 106 using the hardmask 108 and the hardmask 107 as a mask, wiring trenches 117 are formed and at the same time, the via holes 111 are extended to the wirings 102.
Thereafter, a barrier metal film and a Cu-seed layer (not shown) are formed on the whole surface, on which a Cu-film is formed by an electroplating. Then, CMP of the Cu-film, the Cu-seed layer, the barrier metal film, and the hardmask 108 is performed until the hardmask 107 is exposed. As a result, as shown in FIGS. 12J and 13, a structure in which vias 118a are buried in the via holes 111, and wirings 118b are buried in the wiring trenches 117 is obtained. FIG. 13 is the cross sectional view of FIG. 12J taken along the line III-III.
Conventionally, the Cu wirings are formed by this method, however, withstand voltage between adjacent vias 118a is not sufficient.
Note that forming an inorganic protection film on the side wall of the via holes by CVD method is disclosed in the patent documents 1 and 2, however, forming the inorganic protection film increases the number of the processes, thereby increasing the process time and the cost.
In the patent document 3, forming a protection film after forming the via holes by inversely sputtering a base film is disclosed, however, forming the protection film increases the number of the process, thereby increasing the process time and the cost.
In the patent document 4, adjusting an atmosphere during ashing a resistmask used for forming contact holes which extend to electrodes of a ferroelectric capacitor is disclosed. However, it is not the technologies relating to a part where a problem of a withstand voltage occurs, and it is impossible to suppress the reduction in the withstand voltage through these adjusting.
Related arts are disclosed in:
patent document 1 (Japanese Patent Application Laid-open No. 2004-119950),
patent document 2 (Japanese Patent Application Laid-open No.Hei 10-284600),
patent document 3 (Japanese Patent Application Laid-open No. 2000-183040), and
patent document 4 (Japanese Patent Application Laid-open No. 2003-7981).